The present invention relates to a complementary metal-oxide semiconductor (CMOS) fabrication process. More particularly, the present invention relates to a CMOS fabrication process using dual-doped gate structures.
Ultra-large-scale integrated (ULSI) circuits often include more than one million CMOS transistors. The transistors can have gate lengths of less than 0.25 microns (e.g., deep submicrometer devices). The transistors typically have polysilicon gate conductors disposed between drains and sources. The polysilicon gate conductors are heavily doped for increased conductivity.
The polysilicon gate conductors can be dual-doped gate structures where the gate structures are heavily doped with N-type dopants (N+) for N-channel metal-oxide semiconductor field effect transistors (MOSFETS) and are heavily doped with P-type dopants (P+) for P-channel MOSFETS. Utilizing a dual-doped gate structure allows the active regions associated with the N-channel and P-channel MOSFETS and the polysilicon gate structures associated with the MOSFETS to be advantageously doped during the same process steps.
Dual-doped gate structures are susceptible to mutual diffusion. For example, the dopant in an N-type portion of the gate can diffuse into the adjacent P-type portion of the gate. Alternatively, the dopant in the P-type gate can diffuse into an adjacent N-type portion of the gate. Dopant mutual diffusion causes dopant compensation in regions where the N-type portion of the gate meets or neighbors a P-type portion of the gate. Dopant compensation causes several negative effects including severe gate depletion, reduction of effective channel width, and an increase of gate sheet resistance. Severe gate depletion, which occurs near the interface of the polysilicon and gate dielectric, degrades the transistor drive current and hence reduces circuit speed. Similarly, reduction of the effective gate width causes degradation of transistor drive current and hence reduction of circuit speed. Increased gate sheet resistance also degrades the speed of the transistor.
In conventional processes, mutual diffusion of the dopants in the dual-doped gate structures is suppressed by spacing N-active and P-active regions and N-well and P-well regions sufficiently far apart. However, such a solution can significantly reduce the packing density of integrated circuits and hence, the number of transistors which can be provided on an integrated circuit (IC).
Thus, there is a need for a dual-doped gate structure which is not susceptible to mutual diffusion and which does not require large spacings between N and P regions. Further still, there is a need for a process for making such a structure. Even further still, there is a need for a dual-doped gate structure which can be efficiently produced in a compacted structure.
The present invention relates to a method of manufacturing an integrated circuit including a plurality of first transistors and a plurality of second transistors. The first transistors have first gates doped with first type dopants. The second transistors have second gates doped with second type dopants. The method includes selectively implanting inert ions into a polysilicon layer at locations, selectively doping the polysilicon layer with the first type dopants for the first gates, and selectively doping the polysilicon layer with the second type dopants for the second gates. The locations are between the first gates and the second gates. The inert ions suppress dopant diffusion.
The present invention still further relates to a method of manufacturing an integrated circuit having an isolation region between a P+ gate conductor region and an N+ gate conductor region. The method includes providing a first photoresist layer over a substrate having a gate conductor layer, exposing the substrate to inert ions to provide the inert ions to the isolation region, providing a second photoresist layer exclusive of the P+ gate conductor region, exposing the substrate to P dopants to provide the P dopants to the P+ conductor region, providing a third photoresist layer exclusive of the N gate conductor region, and exposing the substrate to N dopants to provide the N dopants to the N+ conductor region.
The present invention still further relates to a method of manufacturing an ultra-large-scale integrated circuit having P-channel field effect transistors with heavily doped P-type polysilicon gates and N-channel field effect transistors having heavily doped N-type polysilicon gates. The method includes providing a polysilicon gate layer and implanting inert ions in the polysilicon gate layer at locations between the N-channel field effect transistors and the P-channel field effect transistors.